• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • A2F060M3F-1CS288YI PDF文件及第1页内容在线浏览

A2F060M3F-1CS288YI

A2F060M3F-1CS288YI首页预览图
型号: A2F060M3F-1CS288YI
PDF文件:
  • A2F060M3F-1CS288YI PDF文件
  • A2F060M3F-1CS288YI PDF在线浏览
功能描述: SmartFusion Customizable System-on-Chip (cSoC)
PDF文件大小: 11779.94 Kbytes
PDF页数: 共192页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝A2F060M3F-1CS288YI
PDF页面索引
[1] 页[2] 页[3] 页[4] 页[5] 页[6] 页[7] 页[8] 页[9] 页[10] 页[11] 页[12] 页[13] 页[14] 页[15] 页[16] 页[17] 页[18] 页[19] 页[20] 页[21] 页[22] 页[23] 页[24] 页[25] 页[26] 页[27] 页[28] 页[29] 页[30] 页[31] 页[32] 页[33] 页[34] 页[35] 页[36] 页[37] 页[38] 页[39] 页[40] 页[41] 页[42] 页[43] 页[44] 页[45] 页[46] 页[47] 页[48] 页[49] 页[50] 页[51] 页[52] 页[53] 页[54] 页[55] 页[56] 页[57] 页[58] 页[59] 页[60] 页[61] 页[62] 页[63] 页[64] 页[65] 页[66] 页[67] 页[68] 页[69] 页[70] 页[71] 页[72] 页[73] 页[74] 页[75] 页[76] 页[77] 页[78] 页[79] 页[80] 页[81] 页[82] 页[83] 页[84] 页[85] 页[86] 页[87] 页[88] 页[89] 页[90] 页[91] 页[92] 页[93] 页[94] 页[95] 页[96] 页[97] 页[98] 页[99] 页[100] 页[101] 页[102] 页[103] 页[104] 页[105] 页[106] 页[107] 页[108] 页[109] 页[110] 页[111] 页[112] 页[113] 页[114] 页[115] 页[116] 页[117] 页[118] 页[119] 页[120] 页[121] 页[122] 页[123] 页[124] 页[125] 页[126] 页[127] 页[128] 页[129] 页[130] 页[131] 页[132] 页[133] 页[134] 页[135] 页[136] 页[137] 页[138] 页[139] 页[140] 页[141] 页[142] 页[143] 页[144] 页[145] 页[146] 页[147] 页[148] 页[149] 页[150] 页[151] 页[152] 页[153] 页[154] 页[155] 页[156] 页[157] 页[158] 页[159] 页[160] 页[161] 页[162] 页[163] 页[164] 页[165] 页[166] 页[167] 页[168] 页[169] 页[170] 页[171] 页[172] 页[173] 页[174] 页[175] 页[176] 页[177] 页[178] 页[179] 页[180] 页[181] 页[182] 页[183] 页[184] 页[185] 页[186] 页[187] 页[188] 页[189] 页[190] 页[191] 页[192] 页
120%
January 2013 I
© 2013 Microsemi Corporation
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS)
Hard 100 MHz 32-Bit ARM
®
Cortex™-M3
1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
Memory Protection Unit (MPU)
Single Cycle Multiplication, Hardware Divide
JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
Internal Memory
Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Multi-Layer AHB Communications Matrix
Provides up to 16 Gbps of On-Chip Memory
Bandwidth,
1
Allowing Multi-Master Schemes
10/100 Ethernet MAC with RMII Interface
2
Programmable External Memory Controller, Which
Supports:
Asynchronous Memories
NOR Flash, SRAM, PSRAM
Synchronous SRAMs
•Two I
2
C Peripherals
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-Bit Timers
32-Bit Watchdog Timer
8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
Clock Sources
32 KHz to 20 MHz Main Oscillator
Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
100 MHz Embedded RC Oscillator; 1% Accurate
Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
High-Performance FPGA
Based on proven ProASIC
®
3 FPGA Fabric
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Instant On, Retains Program When
Powered Off
350 MHz System Performance
Embedded SRAMs and FIFOs
Variable Aspect Ratio 4,608-Bit SRAM Blocks
x1, x2, x4, x9, and x18 Organizations
True Dual-Port SRAM (excluding x18)
Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock
®
to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
Programmable Analog
Analog Front-End (AFE)
Up to Three 12-Bit SAR ADCs
500 Ksps in 12-Bit Mode
550 Ksps in 10-Bit Mode
600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order  DAC (sigma-delta) per ADC
8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
Up to Ten High-Speed Voltage Comparators
(t
pd
=15ns)
Analog Compute Engine (ACE)
Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Engine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero
®
System-on-Chip
(SoC) Software
I/Os and Operating Voltage
FPGA I/Os
LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
Up to 350 MHz
MSS I/Os
Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
1 Theoretical maximum
2 A2F200 and larger devices
Revision 10
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价