SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-75
Timing Characteristics
Embedded Nonvolatile Memory Block (eNVM)
Electrical Characteristics
Table 2-90 describes the eNVM maximum performance.
Table 2-89 • FIFO
Worst Commercial-Case Conditions: T
J
= 85°C, VCC = 1.425 V
Parameter Description –1 Std. Units
t
ENS
REN, WEN Setup Time 1.40 1.68 ns
t
ENH
REN, WEN Hold Time 0.02 0.02 ns
t
BKS
BLK Setup Time 0.19 0.19 ns
t
BKH
BLK Hold Time 0.00 0.00 ns
t
DS
Input Data (WD) Setup Time 0.19 0.22 ns
t
DH
Input Data (WD) Hold Time 0.00 0.00 ns
t
CKQ1
Clock High to New Data Valid on RD (flow-through) 2.39 2.87 ns
t
CKQ2
Clock High to New Data Valid on RD (pipelined) 0.91 1.09 ns
t
RCKEF
RCLK High to Empty Flag Valid 1.74 2.09 ns
t
WCKFF
WCLK High to Full Flag Valid 1.66 1.99 ns
t
CKAF
Clock HIGH to Almost Empty/Full Flag Valid 6.29 7.54 ns
t
RSTFG
RESET Low to Empty/Full Flag Valid 1.72 2.06 ns
t
RSTAF
RESET Low to Almost Empty/Full Flag Valid 6.22 7.47 ns
t
RSTBQ
RESET Low to Data Out Low on RD (flow-through) 0.94 1.12 ns
RESET Low to Data Out Low on RD (pipelined) 0.94 1.12 ns
t
REMRSTB
RESET Removal 0.29 0.35 ns
t
RECRSTB
RESET Recovery 1.52 1.83 ns
t
MPWRSTB
RESET Minimum Pulse Width 0.22 0.22 ns
t
CYC
Clock Cycle Time 3.28 3.28 ns
F
MAX
Maximum Frequency for FIFO 305 305 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: T
J
= 85°C, VCC = 1.425 V
Parameter Description
A2F060 A2F200 A2F500
Units–1 Std. –1 Std. –1 Std.
t
FMAXCLKeNVM
Maximum frequency for clock for the control logic – 5
cycles (5:1:1:1*)
80 80 80 80 50 50 MHz
t
FMAXCLKeNVM
Maximum frequency for clock for the control logic – 6
cycles (6:1:1:1*)
100 80 100 80 100 80 MHz
Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles
for the first access and 1 each for the next three accesses.