SmartFusion DC and Switching Characteristics
2-52 Revision 10
Timing Characteristics
Figure 2-20 • Input DDR Timing Diagram
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
t
DDRICLR2Q1
12 3 4 5 6 7 8 9
CLK
Data
CLR
Out_QR
Out_QF
t
DDRICLKQ1
2
4
6
3
5
7
t
DDRIHD
t
DDRISUD
t
DDRICLKQ2
Table 2-75 • Input DDR Propagation Delays
Worst Commercial-Case Conditions: T
J
= 85°C, Worst Case VCC = 1.425 V
Parameter Description –1 Units
t
DDRICLKQ1
Clock-to-Out Out_QR for Input DDR 0.39 ns
t
DDRICLKQ2
Clock-to-Out Out_QF for Input DDR 0.28 ns
t
DDRISUD
Data Setup for Input DDR 0.29 ns
t
DDRIHD
Data Hold for Input DDR 0.00 ns
t
DDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR 0.58 ns
t
DDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR 0.47 ns
t
DDRIREMCLR
Asynchronous Clear Removal time for Input DDR 0.00 ns
t
DDRIRECCLR
Asynchronous Clear Recovery time for Input DDR 0.23 ns
t
DDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 ns
t
DDRICKMPWH
Clock Minimum Pulse Width High for Input DDR 0.36 ns
t
DDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR 0.32 ns
F
DDRIMAX
Maximum Frequency for Input DDR 350 MHz
Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for
derating values.