SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-31
Timing Characteristics
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
t
ZLS
t
ZHS
Units
4 mA Std. 0.60 7.20 0.04 0.97 0.39 7.34 6.18 2.52 2.46 9.39 8.23 ns
–1 0.50 6.00 0.03 0.81 0.32 6.11 5.15 2.10 2.05 7.83 6.86 ns
8 mA Std. 0.60 4.64 0.04 0.97 0.39 4.73 3.84 2.85 3.02 6.79 5.90 ns
–1 0.50 3.87 0.03 0.81 0.32 3.94 3.20 2.37 2.52 5.65 4.91 ns
12 mA Std. 0.60 3.37 0.04 0.97 0.39 3.43 2.67 3.07 3.39 5.49 4.73 ns
–1 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns
16 mA Std. 0.60 3.18 0.04 0.97 0.39 3.24 2.43 3.11 3.48 5.30 4.49 ns
–1 0.50 2.65 0.03 0.81 0.32 2.70 2.03 2.59 2.90 4.42 3.74 ns
24 mA Std. 0.60 2.93 0.04 0.97 0.39 2.99 2.03 3.17 3.83 5.05 4.09 ns
–1 0.50 2.45 0.03 0.81 0.32 2.49 1.69 2.64 3.19 4.21 3.41 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
t
ZLS
t
ZHS
Units
4 mA Std. 0.60 9.75 0.04 0.97 0.39 9.93 8.22 2.52 2.31 11.99 10.28 ns
–1 0.50 8.12 0.03 0.81 0.32 8.27 6.85 2.10 1.93 9.99 8.57 ns
8 mA Std. 0.60 6.96 0.04 0.97 0.39 7.09 5.85 2.84 2.87 9.15 7.91 ns
–1 0.50 5.80 0.03 0.81 0.32 5.91 4.88 2.37 2.39 7.62 6.59 ns
12 mA Std. 0.60 5.35 0.04 0.97 0.39 5.45 4.58 3.06 3.23 7.51 6.64 ns
–1 0.50 4.46 0.03 0.81 0.32 4.54 3.82 2.55 2.69 6.26 5.53 ns
16 mA Std. 0.60 5.01 0.04 0.97 0.39 5.10 4.30 3.11 3.32 7.16 6.36 ns
–1 0.50 4.17 0.03 0.81 0.32 4.25 3.58 2.59 2.77 5.97 5.30 ns
24 mA Std. 0.60 4.67 0.04 0.97 0.39 4.75 4.28 3.16 3.66 6.81 6.34 ns
–1 0.50 3.89 0.03 0.81 0.32 3.96 3.57 2.64 3.05 5.68 5.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to MSS I/O Banks
Drive
Strength
Speed
Grade t
DOUT
t
DP
t
DIN
t
PY
t
PYS
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
8 mA Std. 0.22 2.31 0.09 0.94 1.30 0.22 2.35 1.86 2.20 2.45 ns
–1 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.