SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-15
Standby Mode
P
DYN
= P
RC-OSC
+ P
LPXTAL-OSC
Time Keeping Mode
P
DYN
= P
LPXTAL-OSC
Global Clock Dynamic Contribution—P
CLOCK
SoC Mode
P
CLOCK
= (P
AC1
+ N
SPINE
* P
AC2
+ N
ROW
* PAC3 + N
S-CELL
* P
AC4
) * F
CLK
N
SPINE
is the number of global spines used in the user design—guidelines are provided in the
"Device Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.
N
ROW
is the number of VersaTile rows used in the design—guidelines are provided in the "Device
Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.
F
CLK
is the global clock signal frequency.
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
Standby Mode and Time Keeping Mode
P
CLOCK
= 0 W
Sequential Cells Dynamic Contribution—P
S-CELL
SoC Mode
P
S-CELL
= N
S-CELL
* (P
AC5
+ (
1
/ 2) * P
AC6
) * F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.
F
CLK
is the global clock signal frequency.
Standby Mode and Time Keeping Mode
P
S-CELL
= 0 W
Combinatorial Cells Dynamic Contribution—P
C-CELL
SoC Mode
P
C-CELL
= N
C-CELL
* (
1
/ 2) * P
AC7
* F
CLK
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.
F
CLK
is the global clock signal frequency.
Standby Mode and Time Keeping Mode
P
C-CELL
= 0 W
Routing Net Dynamic Contribution—P
NET
SoC Mode
P
NET
= (N
S-CELL
+ N
C-CELL
) * (
1
/ 2) * P
AC8
* F
CLK
N
S-CELL
is the number VersaTiles used as sequential modules in the design.
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.
F
CLK
is the frequency of the clock driving the logic including these nets.