SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-9
EQ 6
The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the
airflow where the device is mounted should be increased. The design's total junction-to-air thermal
resistance requirement can be estimated by EQ 7:
EQ 7
Determining the heat sink's thermal performance proceeds as follows:
EQ 8
where
EQ 9
A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat
sinks is a function of airflow. The heat sink performance can be significantly improved with increased
airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design
engineers should always correlate the power consumption of the device with the maximum allowable
power dissipation of the package selected for that device.
Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard
(JESD-51) and assumptions made in building the model. It may not be realized in actual
application and therefore should be used with a degree of caution. Junction-to-case thermal
resistance assumes that all power is dissipated through the case.
Temperature and Voltage Derating Factors
JA
= 0.37°C/W
= Thermal resistance of the interface material between
the case and the heat sink, usually provided by the
thermal interface manufacturer
SA
= Thermal resistance of the heat sink in °C/W
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to T
J
= 85°C, worst-case VCC = 1.425 V)
Array
Voltage VCC
(V)
Junction Temperature (°C)
–40°C 0°C 25°C 70°C 85°C 100°C
1.425 0.86 0.91 0.93 0.98 1.00 1.02
1.500 0.81 0.86 0.88 0.93 0.95 0.96
1.575 0.78 0.83 0.85 0.90 0.91 0.93
P
T
J
T
A
–
JA
-------------------
100°C 70°C–
17.00 W
----------------------------------- -
1.76 W== =
JA(total)
T
J
T
A
–
P
-------------------
100°C 70°C–
3.00 W
----------------------------------- -
10.00°C/W== =
SA
13.33°C/W 8.28°C/W– 0.37°C/W– 5.01°C/W==