Pin Descriptions
5-4 Revision 10
VJTAG Supply Digital supply to the JTAG controller
SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins
can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power
supply in a separate I/O bank gives greater flexibility in supply selection and simplifies
power supply and PCB design. If the JTAG interface is neither used nor planned to be
used, the V
JTAG
pin together with the TRSTB pin could be tied to GND. Note that VCC
is required to be powered for JTAG operation; VJTAG alone is insufficient. If a
SmartFusion cSoC is in a JTAG chain of interconnected boards and it is desired to
power down the board containing the device, this can be done provided both VJTAG
and VCC to the device remain powered; otherwise, JTAG signals will not be able to
transition the device, even in bypass mode. See "JTAG Pins" section on page 5-10.
VPP Supply Digital programming circuitry supply
SmartFusion cSoCs support single-voltage in-system programming (ISP) of the
configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile
memory (eNVM).
For programming, VPP should be in the 3.3 V ± 5% range. During normal device
operation, VPP can be left floating or can be tied to any voltage between 0 V and 3.6 V.
When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no
sources of oscillation from the charge pump circuitry. For proper programming, 0.01μF,
and 0.1μF to 1μF capacitors, (both rated at 16 V) are to be connected in parallel across
VPP and GND, and positioned as close to the FPGA pins as possible.
Name Type Description
Notes:
1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC15A, and VCC15ADCx.
3. For more details on VCCPLLx capacitor recommendations, refer to the application note AC359, SmartFusion cSoC
Board Design Guidelines, the "PLL Power Supply Decoupling Scheme" section.
