SmartFusion Programming
4-8 Revision 10
The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAGSEL is
asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset
state (logic 0), as depicted in Figure 4-1. Users should tie the JTAGSEL pin high externally.
Microsemi’s free Eclipse-based IDE, SoftConsole, has the ability to control the JTAGSEL pin directly with
the FlashPro4 programmer. Manual jumpers are provided on the evaluation and development kits to
allow manual selection of this function for the J-Link and ULINK debuggers.
Note: Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoftConsole
automatically selects the appropriate TAP controller using the CTXSELECT JTAG command.
When using SoftConsole, the state of JTAGSEL is a "don't care."
In-Application Programming
In-application programming refers to the ability to reprogram the various flash areas under direct
supervision of the Cortex-M3.
Reprogramming the FPGA Fabric Using the Cortex-M3
In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be
incorporated into the design project and executed from eNVM or eSRAM. The SoC Products Group
provides working example projects for SoftConsole, IAR, and Keil development environments. These can
be downloaded via the SoC Products Group Firmware Catalog. The new bitstream to be programmed
into the FPGA can reside on the user’s printed circuit board (PCB) in a separate SPI flash memory.
Alternately, the user can modify the existing projects supplied by the SoC Products Group and, via
custom handshaking software, throttle the download of the new image and program the FPGA a piece at
a time in real time. A cost-effective and reliable approach would be to store the bitstream in an external
SPI flash. Another option is storing a redundant bitstream image in an external SPI flash and loading the
newest version into the FPGA only when receiving an IAP command. Since the FPGA I/Os are tristated
or held at predefined or last known state during FPGA programming, the user must use MSS I/Os to
interface to external memories. Since there are two SPI controllers in the MSS, the user can dedicate
one to an SPI flash and the other to the particulars of an application. The amount of flash memory
required to program the FPGA always exceeds the size of the eNVM block that is on-chip. The external
memory controller (EMC) cannot be used as an interface to a memory device for storage of a bitstream
because its I/O pads are FPGA I/Os; hence they are tristated when the FPGA is in a programming state.
The MSS resets itself after IAP of the FPGA fabric. This reset is internally asserted on MSS_RESETN by
the power supply monitor (PSM) and reset controller of the MSS.
Figure 4-1 • TRSTB Logic
JTAG_SEL
TRSTB
Cortex-M3
TAP
Controller
FPGA
Programming Control
FPGA TAP
Controller
TRSTB
VJTAG (1.5 V to 3.3. V nominal)
