SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-57
Timing Characteristics
VersaTile Specifications as a Sequential Module
The SmartFusion library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented
for a representative sample from the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E,
and SmartFusion Macro Library Guide.
Table 2-78 • Combinatorial Cell Propagation Delays
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V
Combinatorial Cell Equation Parameter –1 Std. Units
INV Y = !A t
PD
0.41 0.49 ns
AND2 Y = A · B t
PD
0.48 0.57 ns
NAND2 Y = !(A · B) t
PD
0.48 0.57 ns
OR2 Y = A + B t
PD
0.49 0.59 ns
NOR2 Y = !(A + B) t
PD
0.49 0.59 ns
XOR2 Y = A Bt
PD
0.75 0.90 ns
MAJ3 Y = MAJ(A, B, C) t
PD
0.71 0.85 ns
XOR3 Y = A
B Ct
PD
0.89 1.07 ns
MUX2 Y = A !S + B S t
PD
0.51 0.62 ns
AND3 Y = A · B · C t
PD
0.57 0.68 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for
derating values.
Figure 2-25 • Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
D
Q
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
D
Q
DFN1E1
Data
CLK
Out
En