SmartFusion Customizable System-on-Chip (cSoC)
Revision 10 2-49
Output Register
Timing Characteristics
Figure 2-17 • Output Register Timing Diagram
Preset
Clear
DOUT
CLK
Data_out
Enable
t
OSUE
50%
50%
t
OSUD
t
OHD
50%
50%
t
OCLKQ
1
0
t
OHE
t
ORECPRE
t
OREMPRE
t
ORECCLR
t
OREMCLR
t
OWCLR
t
OWPRE
t
OPRE2Q
t
OCLR2Q
t
OCKMPWH
t
OCKMPWL
50%
50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
50%
Table 2-72 • Output Data Register Propagation Delays
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
t
OCLKQ
Clock-to-Q of the Output Data Register 0.60 0.72 ns
t
OSUD
Data Setup Time for the Output Data Register 0.32 0.38 ns
t
OHD
Data Hold Time for the Output Data Register 0.00 0.00 ns
t
OSUE
Enable Setup Time for the Output Data Register 0.44 0.53 ns
t
OHE
Enable Hold Time for the Output Data Register 0.00 0.00 ns
t
OCLR2Q
Asynchronous Clear-to-Q of the Output Data Register 0.82 0.98 ns
t
OPRE2Q
Asynchronous Preset-to-Q of the Output Data Register 0.82 0.98 ns
t
OREMCLR
Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns
t
ORECCLR
Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns
t
OREMPRE
Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns
t
ORECPRE
Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns
t
OWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.22 ns
t
OWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.22 ns
t
OCKMPWH
Clock Minimum Pulse Width High for the Output Data Register 0.36 0.36 ns
t
OCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.32 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2- 7 on
page 2-9 for derating values.