SmartFusion DC and Switching Characteristics
2-48 Revision 10
Input Register
Timing Characteristics
Figure 2-16 • Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
t
ISUE
50%
50%
t
ISUD
t
IHD
50%
50%
t
ICLKQ
1
0
t
IHE
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH
t
ICKMPWL
50%
50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
Table 2-71 • Input Data Register Propagation Delays
Worst Commercial-Case Conditions: T
J
= 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
t
ICLKQ
Clock-to-Q of the Input Data Register 0.24 0.29 ns
t
ISUD
Data Setup Time for the Input Data Register 0.27 0.32 ns
t
IHD
Data Hold Time for the Input Data Register 0.00 0.00 ns
t
ISUE
Enable Setup Time for the Input Data Register 0.38 0.45 ns
t
IHE
Enable Hold Time for the Input Data Register 0.00 0.00 ns
t
ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register 0.46 0.55 ns
t
IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register 0.46 0.55 ns
t
IREMCLR
Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns
t
IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register 0.23 0.27 ns
t
IREMPRE
Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns
t
IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns
t
IWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.22 ns
t
IWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.22 ns
t
ICKMPWH
Clock Minimum Pulse Width High for the Input Data Register 0.36 0.36 ns
t
ICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.32 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9
for derating values.