SmartFusion DC and Switching Characteristics
2-16 Revision 10
Standby Mode and Time Keeping Mode
P
NET
= 0 W
I/O Input Buffer Dynamic Contribution—P
INPUTS
SoC Mode
P
INPUTS
= N
INPUTS
* (
2
/ 2) * P
AC9
* F
CLK
Where:
N
INPUTS
is the number of I/O input buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.
F
CLK
is the global clock signal frequency.
Standby Mode and Time Keeping Mode
P
INPUTS
= 0 W
I/O Output Buffer Dynamic Contribution—P
OUTPUTS
SoC Mode
P
OUTPUTS
= N
OUTPUTS
* (
2
/ 2) *
1
* P
AC10
* F
CLK
Where:
N
OUTPUTS
is the number of I/O output buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.
1
is the I/O buffer enable rate—guidelines are provided in Table 2-18 on page 2-18.
F
CLK
is the global clock signal frequency.
Standby Mode and Time Keeping Mode
P
OUTPUTS
= 0 W
FPGA Fabric SRAM Dynamic Contribution—P
MEMORY
SoC Mode
P
MEMORY
= (N
BLOCKS
* P
AC11
*
2
* F
READ-CLOCK
) + (N
BLOCKS
* P
AC12
*
3
* F
WRITE-CLOCK
)
Where:
N
BLOCKS
is the number of RAM blocks used in the design.
F
READ-CLOCK
is the memory read clock frequency.
2
is the RAM enable rate for read operations—guidelines are provided in Table 2-18 on
page 2-18.
3
the RAM enable rate for write operations—guidelines are provided in Table 2-18 on page 2-18.
F
WRITE-CLOCK
is the memory write clock frequency.
Standby Mode and Time Keeping Mode
P
MEMORY
= 0 W
PLL/CCC Dynamic Contribution—P
PLL
SoC Mode
P
PLL
= P
AC13
* F
CLKOUT
F
CLKIN
is the input clock frequency.
F
CLKOUT
is the output clock frequency.
1
Standby Mode and Time Keeping Mode
1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (P
AC14
* F
CLKOUT
product) to the total PLL
contribution.
