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Accelerator Series FPGAs – ACT
™
3 Family
Package Pin Assignments (continued)
133-Pin CPGA (Top View)
133-Pin
CPGA
A
B
C
D
E
F
G
H
J
K
L
M
N
A
B
C
D
E
F
G
H
J
K
L
M
N
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9 10 11 12 13
A1425 Function Location
CLKA or I/O D7
CLKB or I/O B6
DCLK or I/O D4
GND A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12
HCLK or I/O K7
IOCLK or I/O C10
IOPCL or I/O L10
MODE E3
NC A1, A7, A13, G1, G13, N1, N7, N13
PRA OR I/O A6
PRB or I/O L6
SDI or I/O C2
V
CC
B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12
Notes:
1. Unused I/O pins are designated as outputs by ALS and are driven low.
2. All unassigned pins are available for use as I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.