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Hermetic Device Resources
Pin Description
CLKA Clock A (Input)
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
CLKB Clock B (Input)
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
GND Ground
LOW supply voltage.
HCLK Dedicated (Hard-wired)
Array Clock (Input)
Clock input for sequential modules. This input is directly
wired to each S-Module and offers clock speeds independent
of the number of S-Modules being driven. This pin can also be
used as an I/O.
I/O Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are tristated by the Designer Series software.
IOCLK Dedicated (Hard-wired)
I/O Clock (Input)
Clock input for I/O modules. This input is directly wired to
each I/O module and offers clock speeds independent of the
number of I/O modules being driven. This pin can also be
used as an I/O.
IOPCL Dedicated (Hard-wired)
I/O Preset/Clear (Input)
Input for I/O preset or clear. This global input is directly
wired to the preset and clear inputs of all I/O registers. This
pin functions as an I/O when no I/O preset or clear macros
are used.
MODE Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide Actionprobe capability, the
MODE pin should be terminated to GND through a 10K
resistor so that the MODE pin can be pulled high when
required.
NC No Connection
This pin is not connected to circuitry within the device.
PRA Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
DCLK Diagnostic Clock (Input)
Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
V
CC
5 V Supply Voltage
HIGH supply voltage.
Device
Series
Logic
Modules
User I/Os
CPGA CQFP
Gates 100-pin 133-pin 175-pin 207-pin 257-pin 132-pin 196-pin 256-pin
A1415 200 1500 80 — — — — — — —
A1425 310 2500 — 100 — — — 100 — —
A1440 564 4000 — — 140 — — — — —
A1460 848 6000 — — — 168 — — 168 —
A14100 1377 10000 — — — — 228 — — 228
