1-201
Accelerator Series FPGAs – ACT
™
3 Family
A1415A, A14V15A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Note:
1. Delays based on 35pF loading.
I/O Module – TTL Output Timing
1
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
DHS
Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns
t
DLS
Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns
t
ENZHS
Enable to Pad, Z to H/L,
Hi Slew 4.0 4.5 5.1 6.0 7.8 ns
t
ENZLS
Enable to Pad, Z to H/L,
Lo Slew 7.4 8.3 9.4 11.0 14.3 ns
t
ENHSZ
Enable to Pad, H/L to Z,
Hi Slew 6.5 7.5 8.5 10.0 13.0 ns
t
ENLSZ
Enable to Pad, H/L to Z,
Lo Slew 6.5 7.5 8.5 10.0 13.0 ns
t
CKHS
IOCLK Pad to Pad H/L,
Hi Slew 7.5 7.5 9.0 10.0 13.0 ns
t
CKLS
IOCLK Pad to Pad H/L,
Lo Slew 11.3 11.3 13.5 15.0 19.5 ns
d
TLHHS
Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF
d
TLHLS
Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF
d
THLHS
Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF
d
THLLS
Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF
I/O Module – CMOS Output Timing
1
t
DHS
Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns
t
DLS
Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns
t
ENZHS
Enable to Pad, Z to H/L,
Hi Slew 5.2 5.9 6.6 7.8 10.1 ns
t
ENZLS
Enable to Pad, Z to H/L,
Lo Slew 8.9 10.0 11.3 13.3 17.3 ns
t
ENHSZ
Enable to Pad, H/L to Z,
Hi Slew 6.7 7.5 8.5 10.0 13.0 ns
t
ENLSZ
Enable to Pad, H/L to Z,
Lo Slew 6.7 7.5 9.0 10.0 13.0 ns
t
CKHS
IOCLK Pad to Pad H/L,
Hi Slew 8.9 8.9 10.7 11.8 15.3 ns
t
CKLS
IOCLK Pad to Pad H/L,
Lo Slew 13.0 13.0 15.6 17.3 22.5 ns
d
TLHHS
Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF
d
TLHLS
Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF
d
THLHS
Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF
d
THLLS
Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF
