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A14V60AA-1CQ208B

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型号: A14V60AA-1CQ208B
PDF文件:
  • A14V60AA-1CQ208B PDF文件
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功能描述: Accelerator Series FPGAs - ACT 3Family
PDF文件大小: 479.35 Kbytes
PDF页数: 共68页
制造商: ACTEL[Actel Corporation]
制造商LOGO: ACTEL[Actel Corporation] LOGO
制造商网址: http://www.actel.com
捡单宝A14V60AA-1CQ208B
PDF页面索引
120%
1-199
Accelerator Series FPGAs – ACT
3 Family
A1415A, A14V15A Timing Characteristics
(Worst-Case Commercial Conditions, V
CC
= 4.75 V, T
J
= 70°C)
1
Notes:
1. V
CC
= 3.0 V for 3.3V specifications.
2. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
Logic Module Propagation Delays
2
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed
1
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
PD
Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns
t
CO
Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns
t
CLR
Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns
Predicted Routing Delays
3
t
RD1
FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns
t
RD2
FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns
t
RD3
FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns
t
RD4
FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns
t
RD8
FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns
Logic Module Sequential Timing
t
SUD
Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns
t
HD
Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
t
SUD
Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns
t
HD
Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
t
WASYN
Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns
t
WCLKA
Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns
t
A
Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns
f
MAX
Flip-Flop Clock Frequency 250 200 150 125 100 MHz
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