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Accelerator Series FPGAs – ACT
™
3 Family
Sequential Module Timing Characteristics
Flip-Flops
I/O Module: Sequential Input Timing Characteristics
(Positive edge triggered)
D
CLK
CLR
Q
D
CLK
Q
CLR
t
WCLKA
t
WASYN
t
HD
t
SUD
t
A
t
WCLKA
t
CO
t
CLR
(Positive edge triggered)
D
E
IOCLK
CLR
PRE
Y
D
IOCLK
E
Y
PRE, CLR
t
IOPWH
t
IOASPW
t
INH
t
IDESU
t
INSU
t
ICLRY
t
IOP
t
IOPWL
t
ICKY
t
IDEH