1-193
Accelerator Series FPGAs – ACT
™
3 Family
ACT 3 Timing Model*
*Values shown for A1425A-3.
Output DelaysInternal DelaysInput Delays
t
INH
= 0.0 ns
t
INSU
= 1.8 ns
I/O CLOCK
I/O Module
D
Q
t
ICKY
= 4.7 ns
F
IOMAX
= 250 MHz
t
INY
= 2.8 ns
t
IRD2
= 1.2 ns
Combinatorial
Logic Module
t
PD
= 2.0 ns
Sequential
Logic Module
I/O Module
t
RD1
= 0.9 ns
t
DHS
= 5.0 ns
I/O Module
ARRAY
CLOCK
F
HMAX
= 250 MHz
Combin-
atorial
Logic
included
in t
SUD
D
Q
D
Q
t
OUTH
= 0.7 ns
t
OUTSU
= 0.7 ns
t
DHS
= 5.0 ns
t
ENZHS
= 4.0 ns
t
RD1
= 0.9 ns
t
CO
= 2.0 ns
t
SUD
= 0.5 ns
t
HD
= 0.0 ns
t
RD4
= 1.7 ns
t
RD8
= 2.8 ns
Predicted
Routing
Delays
t
HCKH
= 3.0 ns
t
CKHS
= 7.5 ns
(pad-pad)