1-191
Accelerator Series FPGAs – ACT
™
3 Family
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totem-pole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
can be combined with frequency and voltage to represent
active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 2.
Power (uW) = C
EQ
* V
CC
2
* F (2)
Where:
C
EQ
is the equivalent capacitance expressed in pF.
V
CC
is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring I
CC
active
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of V
CC
. Equivalent
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
C
EQ
Values for Actel FPGAs
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 3 shows a piece-wise linear summation
over all components.
Power =V
CC
2 * [(m * C
EQM
* f
m
)
modules
+ (n * C
EQI
* f
n
)
inputs
+ (p * (C
EQO
+ C
L
) * f
p
)
outputs
+ 0.5 * (q
1
* C
EQCR
* f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+ 0.5 * (q
2
* C
EQCR
* f
q2
)
routed_Clk2
+ (r
2
* f
q2
)
routed_Clk2
+ 0.5 * (s
1
*
CEQCD
* f
s1
)
dedicated_Clk
+ (s
2
* CEQCI * f
s2
)
IO_Clk
] (3)
Where:
Modules (C
EQM
) 6.7
Input Buffers (
CEQI
) 7.2
Output Buffers (C
EQO
) 10.4
Routed Array Clock Buffer Loads (C
EQCR
) 1.6
Dedicated Clock Buffer Loads (C
EQCD
) 0.7
I/O Clock Buffer Loads (C
EQCI
) 0.9
m = Number of logic modules switching at f
m
n = Number of input buffers switching at f
n
p = Number of output buffers switching at f
p
q
1
= Number of clock loads on the first routed
array clock
q
2
= Number of clock loads on the second routed
array clock
r
1
= Fixed capacitance due to first routed array
clock
r
2
= Fixed capacitance due to second routed array
clock
s
1
= Fixed number of clock loads on the dedicated
array clock
s
2
= Fixed number of clock loads on the dedicated
I/O clock
C
EQM
= Equivalent capacitance of logic modules in pF
C
EQI
= Equivalent capacitance of input buffers in pF
C
EQO
= Equivalent capacitance of output buffers in
pF
C
EQCR
= Equivalent capacitance of routed array clock
in pF
C
EQCD
= Equivalent capacitance of dedicated array
clock in pF
C
EQCI
= Equivalent capacitance of dedicated I/O clock
in pF
C
L
= Output lead capacitance in pF
f
m
= Average logic module switching rate in MHz
f
n
= Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
f
q1
= Average first routed array clock rate in MHz
f
q2
= Average second routed array clock rate in
MHz
f
s1
= Average dedicated array clock rate in MHz
f
s2
= Average dedicated I/O clock rate in MHz
