1-185
Accelerator Series FPGAs – ACT
™
3 Family
routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array
where edge effects occur. LVTs contain either one or two
segments. An example of vertical routing tracks and
segments is shown in Figure 8.
Figure 7 • Horizontal Routing Tracks and Segments
Figure 8 • Vertical Routing Tracks and Segments
HF
MODULE ROW
HCLK
CLK0
NVCC
SIGNAL
SIGNAL
(LHT)
SIGNAL
NVSS
CLK1
TRACK
SEGMENT
|
|
|
|
|
|
|
MODULE ROW
VERTICLE INPUT
SEGMENT
S-MODULE C-MODULE
VF
FF
XF
MODULE ROW
CHANNEL
LVTS
S-MODULE C-MODULE