v4.0 9
ACT
™
2 Family FPGAs
Sequential Module Timing Characteristics
Flip-Flops and Latches
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
(Positive edge triggered)
D
E
CLK
CLR
PRE
Y
D
1
G, CLK
E
Q
PRE, CLR
t
WCLKA
t
WASYN
t
HD
t
SUENA
t
SUD
t
RS
t
A
t
WCLKI
t
CO
t
HENA