v4.0 7
ACT
™
2 Family FPGAs
ACT 2 Timing Model*
*Values shown for A1240A-2 at worst-case commercial conditions. † Input Module Predicted Routing Delay
Output DelaysInternal DelaysInput Delays
t
INH
= 2.0 ns
t
INSU
= 4.0 ns
I/O Module
D
Q
t
INGL
= 4.7 ns
t
INYL
= 2.6 ns
t
IRD2
= 4.8 ns†
Combinatorial
Logic Module
t
PD
= 3.8 ns
Sequential
Logic Module
I/O Module
t
RD1
= 1.4 ns
t
DLH
= 8.0 ns
I/O Module
ARRAY
CLOCKS
F
MAX
= 100 MHz
Combin-
atorial
Logic
included
in t
SUD
D
Q
D
Q
t
OUTH
= 0.0 ns
t
OUTSU
= 0.4 ns
t
GLH
= 9.0 ns
t
DLH
= 8.0 ns
t
ENHZ
= 7.1 ns
t
RD1
= 1.4 ns
t
CO
= 3.8 ns
t
SUD
= 0.4 ns
t
HD
= 0.0 ns
t
RD4
= 3.1 ns
t
RD8
= 4.7 ns
Predicted
Routing
Delays
t
CKH
= 11.8 ns
G
G
FO = 256
t
RD2
= 1.7 ns
