ACT
™
2 Family FPGAs
6v4.0
and load device inputs. An additional component of the
active power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (
µW) = C
EQ
* V
CC
2
* F (1)
Where:
C
EQ
is the equivalent capacitance expressed in pF.
V
CC
is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC
active at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results
may be used over a wide range of operating conditions.
Equivalent capacitance values are shown below.
C
EQ
Values for Actel FPGAs
Modules (C
EQM
)5.8
Input Buffers (C
EQI
) 12.9
Output Buffers (C
EQO
) 23.8
Routed Array Clock Buffer Loads (C
EQCR
)3.9
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Power = V
CC
2
* [(m * C
EQM
* f
m
)
modules
+(n * C
EQI
* f
n
)
inputs
+ (p * (C
EQO
+ C
L
) * f
p
)
outputs
+ 0.5 * (q
1
* C
EQCR
*
f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+ 0.5 * (q
2
* C
EQCR
*
f
q2
)
routed_Clk2
+ (r
2
* f
q2
)
routed_Clk2
](2)
Where:
Fixed Capacitance Values for Actel FPGAs
(pF)
r1 r2
Device Type routed_Clk1 routed_Clk2
A1225A 106 106.0
A1240A 134 134.2
A1280A 168 167.8
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array
clock
q2 = Number of clock loads on the second routed
array clock
r
1
= Fixed capacitance due to first routed array
clock
r
2
= Fixed capacitance due to second routed array
clock
C
EQM
= Equivalent capacitance of logic modules in pF
C
EQI
= Equivalent capacitance of input buffers in pF
C
EQO
= Equivalent capacitance of output buffers in pF
C
EQCR
= Equivalent capacitance of routed array clock in
pF
C
L
= Output lead capacitance in pF
f
m
= Average logic module switching rate in MHz
f
n
= Average input buffer switching rate in MHz
f
p
= Average output buffer switching rate in MHz
f
q1
= Average first routed array clock rate in MHz
f
q2
= Average second routed array clock rate in MHz
Logic Modules (m) 80% of modules
Inputs switching (n) # inputs/4
Outputs switching (p) # outputs/4
First routed array clock loads (q
1
) 40%of
sequential
modules
Second routed array clock loads (q
2
) 40%of
sequential
modules
Load capacitance (C
L
) 35 pF
Average logic module switching rate (f
m
)F/10
Average input switching rate (f
n
)F/5
Average output switching rate (f
p
)F/10
Average first routed array clock rate (f
q1
)F
Average second routed array clock rate
(f
q2
)
F/2
