v4.0 19
ACT
™
2 Family FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Units
t
INYH
Pad to Y High 2.9 3.3 3.8 ns
t
INYL
Pad to Y Low 2.7 3.0 3.5 ns
t
INGH
G to Y High 5.0 5.7 6.6 ns
t
INGL
G to Y Low 4.8 5.4 6.3 ns
Input Module Predicted Routing Delays
1
t
IRD1
FO=1 Routing Delay 4.6 5.1 6.0 ns
t
IRD2
FO=2 Routing Delay 5.2 5.9 6.9 ns
t
IRD3
FO=3 Routing Delay 5.6 6.3 7.4 ns
t
IRD4
FO=4 Routing Delay 6.5 7.3 8.6 ns
t
IRD8
FO=8 Routing Delay 9.4 10.5 12.4 ns
Global Clock Network
t
CKH
Input Low to High
FO = 32
FO = 384
10.2
13.1
11.0
14.6
12.8
17.2
ns
t
CKL
Input High to Low
FO = 32
FO = 384
10.2
13.3
11.0
14.9
12.8
17.5
ns
t
PWH
Minimum Pulse Width
High
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
ns
t
PWL
Minimum Pulse Width Low
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
ns
t
CKSW
Maximum Skew
FO = 32
FO = 384
0.5
2.5
0.5
2.5
0.5
2.5
ns
t
SUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
HEXT
Input Latch External Hold
FO = 32
FO = 384
7.0
11.2
7.0
11.2
7.0
11.2
ns
t
P
Minimum Period
FO = 32
FO = 384
9.6
10.6
11.2
12.6
13.3
15.3
ns
f
MAX
Maximum Frequency
FO = 32
FO = 384
105.0
95.0
90.0
80.0
75.0
65.0
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
