ACT
™
2 Family FPGAs
16 v4.0
A1240A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Units
t
INYH
Pad to Y High 2.9 3.3 3.8 ns
t
INYL
Pad to Y Low 2.6 3.0 3.5 ns
t
INGH
G to Y High 5.0 5.7 6.6 ns
t
INGL
G to Y Low 4.7 5.4 6.3 ns
Input Module Predicted Routing Delays
1
t
IRD1
FO=1 Routing Delay 4.2 4.8 5.6 ns
t
IRD2
FO=2 Routing Delay 4.8 5.4 6.4 ns
t
IRD3
FO=3 Routing Delay 5.4 6.1 7.2 ns
t
IRD4
FO=4 Routing Delay 5.9 6.7 7.9 ns
t
IRD8
FO=8 Routing Delay 7.9 8.9 10.5 ns
Global Clock Network
t
CKH
Input Low to High
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
t
CKL
Input High to Low
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
ns
t
PWH
Minimum Pulse Width
High
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
ns
t
PWL
Minimum Pulse Width Low
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
ns
t
CKSW
Maximum Skew
FO = 32
FO = 256
0.5
2.5
0.5
2.5
0.5
2.5
ns
t
SUEXT
Input Latch External Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
HEXT
Input Latch External Hold
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
t
P
Minimum Period
FO = 32
FO = 256
8.1
8.8
9.1
10.0
11.1
11.7
ns
f
MAX
Maximum Frequency
FO = 32
FO = 256
125.0
115.0
110.0
100.0
90.0
85.0
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.