ACT
™
2 Family FPGAs
14 v4.0
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing
1
t
DLH
Data to Pad High 8.0 9.0 10.6 ns
t
DHL
Data to Pad Low 10.1 11.4 13.4 ns
t
ENZH
Enable Pad Z to High 8.9 10.0 11.8 ns
t
ENZL
Enable Pad Z to Low 11.6 13.2 15.5 ns
t
ENHZ
Enable Pad High to Z 7.1 8.0 9.4 ns
t
ENLZ
Enable Pad Low to Z 8.3 9.5 11.1 ns
t
GLH
G to Pad High 8.9 10.2 11.9 ns
t
GHL
G to Pad Low 11.2 12.7 14.9 ns
d
TLH
Delta Low to High 0.07 0.08 0.09 ns/pF
d
THL
Delta High to Low 0.12 0.13 0.16 ns/pF
CMOS Output Module Timing
1
t
DLH
Data to Pad High 10.1 11.5 13.5 ns
t
DHL
Data to Pad Low 8.4 9.6 11.2 ns
t
ENZH
Enable Pad Z to High 8.9 10.0 11.8 ns
t
ENZL
Enable Pad Z to Low 11.6 13.2 15.5 ns
t
ENHZ
Enable Pad High to Z 7.1 8.0 9.4 ns
t
ENLZ
Enable Pad Low to Z 8.3 9.5 11.1 ns
t
GLH
G to Pad High 8.9 10.2 11.9 ns
t
GHL
G to Pad Low 11.2 12.7 14.9 ns
d
TLH
Delta Low to High 0.12 0.13 0.16 ns/pF
d
THL
Delta High to Low 0.09 0.10 0.12 ns/pF
Note:
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
