v4.0 11
ACT
™
2 Family FPGAs
Timing Derating Factor (Temperature and Voltage)
Timing Derating Factor for Designs at Typical Temperature (T
J
= 25°C) and
Voltage (5.0 V)
Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, T
J
= 4.75 V, 70°C)
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, T
J
= 4.75V, 70°C)
Industrial Military
Min. Max. Min. Max.
(Commercial Minimum/Maximum Specification) x 0.69 1.11 0.67 1.23
(Commercial Maximum Specification) x 0.85
–55 –400 257085125
4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23
4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16
5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13
5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09
5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08
Note: This derating factor applies to all routing and propagation delays.
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
4.50 4.75 5.00 5.25 5.50
Derating Factor
Voltage (V)
125˚C
85˚C
70˚C
25˚C
0˚C
–40˚C
–55˚C