2004 Microchip Technology Inc. DS21796D-page 7
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.5 ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY
status of the
device , if CS is brough t high a fter a mi nimum of 250 n s
low ( TCSL).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY
status from
DO.
V
CC must be ≥ 4.5V for proper operation of ERAL.
FIGU RE 2-2 : ERAL TIM IN G
CS
CLK
DI
DO
T
CSL
CHECK STATUS
100 10X
•••
X
T
SV TCZ
BUSY READY
HIGH-Z
T
EC
HIGH-Z