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93C66CTESNG

93C66CTESNG首页预览图
型号: 93C66CTESNG
PDF文件:
  • 93C66CTESNG PDF文件
  • 93C66CTESNG PDF在线浏览
功能描述: 4K Microwire Compatible Serial EEPROM
PDF文件大小: 405.32 Kbytes
PDF页数: 共24页
制造商: MICROCHIP[Microchip Technology]
制造商LOGO: MICROCHIP[Microchip Technology] LOGO
制造商网址: http://www.microchip.com
捡单宝93C66CTESNG
PDF页面索引
120%
2003 Microchip Technology Inc. DS21795B-page 7
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5 ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY
status of the
device , if CS is brough t high a fter a mi nimum of 250 n s
low ( TCSL).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY
status from
DO.
V
CC must be 4.5V for proper operation of ERAL.
FIGU RE 2- 3 : ERAL T IMING F OR 93 AA A ND 9 3L C DEVI C E S
FIGU RE 2-4: ERAL T IM ING FOR 93C DEV ICES
CS
CLK
DI
DO
T
CSL
CHECK STATUS
100 10X
•••
X
T
SV TCZ
BUSY READY
HIGH-Z
T
EC
HIGH-Z
VCC must be 4.5V for proper operation of ERAL.
CS
CLK
DI
DO
T
CSL
CHECK STATUS
100 10X
•••
X
T
SV TCZ
BUSY READY
HIGH-Z
T
EC
HIGH-Z
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