2003 Microchip Technology Inc. DS21795B-page 9
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.8 WRITE
The WRITE instruction is followed by 8 bits (If ORG is
low or A-v ersi on device s) or 16 b its (If OR G pi n is hig h
or B-versi on devices) of data whi ch are writt en into th e
specified address. For 93AA66A/B/C and 93LC66A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programmin g c ycle. F or 93 C66A/ B/C d evices , the se lf-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the READY/BUSY
status of the
device , if CS is brough t high a fter a mi nimum of 250 n s
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY
status from
DO.
FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES
FIGU RE 2-9: WRITE T IM ING FOR 93C DE VICES
CS
CLK
DI
DO
1
0
1An
•••
A0 Dx
•••
D0
BUSY
READY
HIGH-Z
HIGH-Z
Twc
T
CSL
TCZ
TSV
CS
CLK
DI
DO
1
0
1An
•••
A0 Dx
•••
D0
BUSY
READY
HIGH-Z
HIGH-Z
Twc
T
CSL
TCZ
TSV