93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795B-page 10 2003 Microchip Technology Inc.
2.9 WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA66A/ B/C and 93LC66 A/B/C de vices, after th e
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruct ion
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low ( T
CSL).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
V
CC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES
FIGU RE 2-11: WRAL T IM ING FOR 93C DEV ICES
CS
CLK
DI
DO
HIGH-Z
1
0
0
01X
•••
X
Dx
•••
D0
HIGH-Z
BUSY
READY
T
WL
VCC must be ≥ 4.5V for proper operation of WRAL.
TCSL
TSV
TCZ
CS
CLK
DI
DO
HIGH-Z
1
0
0
01X
•••
X
Dx
•••
D0
HIGH-Z
BUSY
READY
T
WL
TCSL
TSV
TCZ
