1©2016 Inte grate d Dev ice T echno logy, Inc Revision B June 28, 2016
General Description
The 831752 is a high -perf orman ce, d iffere ntial HCSL cloc k swi tch.
The device is desi gned for th e routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has on e differe ntial, bi-d irectio nal I/O (FCL K) for
connection to ATCA clock sou rces and to cl ock receiv ers throu gh a
connector. Th e differe ntial clo ck input CLK is the local cloc k input
and the HCSL outpu t Q is the local clock outp ut. In the common
clock mode, FCLK serves as an input and is routed to the differential
HCSL outp ut Q. T here are t wo l ocal clock mode s. In the l ocal cloc k
mode 0, CLK is t he i nput, Q i s the clo ck ou tput a nd FCL K is in
high-impedan ce state. In the local clo ck mode 1, CLK is the input
and both Q and FCLK a re t he ou tput s of t he lo call y gen erate d PCI e
clock signal. The 831752 is character ized to ope rate from a 3. 3V
power or 2.5V power supply. The 831752 supports the switching of
PCI Express (2 .5 Gb/s), Gen 2 (5 Gb /s) and Gen 3 (8 Gb/s) clock
signals.
Features
• Clock switch for PCIe and ATCA/AMC applications
• Supports local and common ATCA/AMC clock modes
• Bi-directional clock I/O FCLK:
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
• Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
• Local HCSL clock output (Q)
• Maximum input/output clock frequency: 500MHz
• Maximum input/output data rate: 1000Mb/s (NRZ)
• LVCMOS interface levels for the control inputs
• PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
• Full 3.3V or 2.5V supply voltage
• Lead-free (RoHS 6) 16-lead TSSOP package
• -40°C to 85°C ambient operating temperature
831752
16-lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package, Top View
Pin Assignment
16 IREF
15 GND
14 VDD
13 Q
12 nQ
11 GND
10 VDD
9 nc
DIR_SEL 1
nOEFCLK 2
VDD 3
FCLK 4
nFCLK 5
GND 6
CLK 7
nCLK 8
Block Diagram
Pulldown
Pullup/Pulldown
Pullup
Pulldown
FCLK
nFCLK
CLK
nCLK
nOEFCLK
DIR_SEL
IREF
1
0
Q
nQ
1=disable
50
50
50
50
22.33
22.33
Clock Switch for ATCA/AMC and PCIe
Applications
831752
Data Sheet
