1/14July 2004
■ 5V TOLERANT INPUTS
■ HIGH S PEED: t
PD
= 6.8ns (MAX.) at V
CC
= 3V
■ POWER DOWN PROTEC TION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PRO PAGATION DELAYS :
t
PLH
≅ t
PHL
■ OPERATI N G VOLTAG E R AN GE:
V
CC
(OPR) = 1.65V to 3 .6V (1.2V Data
Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIE S 374
■ LATCH-UP PERFORMANCE EXCEEDS
500m A (JESD 17)
■ ESD PERFORMANCE:
HB M > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC374A is an advanced high-speed
CMOS OC TA L D -TYP E FLI P FLO P wi t h 3 S TA TE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a clock
input (CK) and an output enable input (OE
).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the ( OE
) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
imp edance s tate.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. Power down protection is
prov ided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V .
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVC374A
OCTAL D-TYPE FL IP-FLOP
HIGH PERFORMANCE
Fi gure 1: Pin Conne ction And IE C Logic S ymb ols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVC374AMTR
TSSOP 74LVC374ATTR
TSSOPSOP
Rev. 2
