1. General description
The 74AHC573-Q100; 74AHCT573-Q100 is a high-speed Si-gate CMOS de vice and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74AHC573-Q100; 74AHCT573-Q100 consists of eight D-type transparent latches
featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (L E) and an outp ut enable input (OE
) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE
is LOW, the contents of the 8 latches are available at the outputs. When
pin OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt trigger action
Common 3-state output enable input
Inputs accept voltages higher tha n V
CC
Input levels:
For 74AHC573-Q100: CMOS input level
For 74AHCT573-Q100: TTL input level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74AHC573-Q100; 74AHCT573-Q100
Octal D-type transparant latch; 3-state
Rev. 1 — 10 June 2013 Product data sheet