1
©2015 Integrated Device Technology, Inc.
JUNE 2018
DSC-4836/5
I/O
Control
Address
Decoder
64Kx16
MEMORY
ARRAY
7028
ARBITRATION
INTERRUPT
SEMAPHO RE
LOGIC
CE
0L
OE
L
R/W
L
A
15L
A
0L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
LB
L
CE
0L
OE
L
UB
L
I/O
Control
Address
Decoder
CE
0R
OE
R
R/W
R
A
15R
A
0R
SEM
R
INT
R
(2)
BUSY
R
(1,2)
LB
R
R/
W
R
OE
R
UB
R
M/S
(2)
CE
1L
CE
0R
CE
1R
4836 drw 01
I/O
CE
1R
CE
1L
8-15L
I/O
I/O
0-7R
I/O
8-15R
0-7L
R/
W
L
16
16
Functional Block Diagram
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆
Interrupt Flag
◆
On-chip port arbitration logic
◆
Full on-chip hardware support of semaphore signaling
between ports
◆
Fully asynchronous operation from either port
◆
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
◆
TTL-compatible, single 5V (±10%) power supply
◆
Available in a 100-pin TQFP
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Green parts available, see ordering information
Features
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆
Low-power operation
– IDT7028L
Active: 1W (typ.)
Standby: 1mW (typ.)
◆
Dual chip enables allow for depth expansion without
external logic
◆
IDT7028 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
HIGH-SPEED
64K x 16 DUAL-PORT
STATIC RAM
IDT7028L
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
