66AK2L06
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SPRS930 –APRIL 2015
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are
not required as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In
addition, error-class events or infrequently used events are also routed through the system event router to
offload the C66x CorePac interrupt selector. This is accomplished through the two CorePac Interrupt
Controller blocks, CIC0 and CIC2. These CIC are clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x
CorePac, ARM GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs
which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3.
CIC1 is reserved. CIC2 has 103 event outputs which provides 8, 20, and 8 events to EDMA3CC0,
EDMA3CC1, and EDMA3C2 respectively.
The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes, from
those EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac.
Modules such as FFTC, CP_MPU (Coprocessor Memory Protection Unit), BOOT_CFG, and CP_Tracer
have level interrupts and EOI handshaking interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and
CP_Tracer.
For FFTC:
• the EOI value is 0 for FFTC_x_INTD_INTR0,
• the EOI value is 1 for FFTC_x_INTD_INTR1,
• the EOI value is 2 for FFTC_x_INTD_INTR2
• the EOI value is 3 for FFTC_x_INTD_INTR3 (where FFTC_x can be FFTC_0 or FFTC_1)
Figure 7-5 shows the 66AK2L06 interrupt topology.
Copyright © 2015, Texas Instruments Incorporated Memory, Interrupts, and EDMA for 66AK2L06 81
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