66AK2L06
www.ti.com
SPRS930 –APRIL 2015
11.1 Recommended Clock and Control Signal Transition
4.4 Power-Down Control ................................ 16
Behavior............................................ 215
4.5 C66x CorePac Revision............................. 17
11.2 Power Supplies .................................... 215
4.6 C66x CorePac Register Descriptions ............... 17
11.3 Power Sleep Controller (PSC) ..................... 222
5 ARM CorePac ........................................... 18
11.4 Reset Controller.................................... 229
5.1 Features ............................................. 19
11.5 PLLs................................................ 233
5.2 System Integration .................................. 19
11.6 DDR3A PLL ........................................ 250
5.3 ARM Cortex-A15 Processor......................... 19
11.7 NETCP PLL ........................................ 252
5.4 CFG Connection .................................... 21
11.8 DFE PLL ........................................... 253
5.5 Main TeraNet Connection........................... 21
11.9 External Interrupts ................................. 257
5.6 Clocking and Reset ................................. 21
11.10 On-Chip Standalone RAM (OSR) ................ 258
6 Terminals ................................................ 22
11.11 DDR3A Memory Controller ....................... 258
6.1 Package Terminals.................................. 22
11.12 I
2
C Peripheral..................................... 260
6.2 Pin Map ............................................. 22
11.13 SPI Peripheral .................................... 264
6.3 Terminal Functions.................................. 27
11.14 UART Peripheral ................................. 267
6.4 Pullup/Pulldown Resistors .......................... 56
11.15 PCIe Peripheral................................... 268
7 Memory, Interrupts, and EDMA for 66AK2L06 ... 57
11.16 Packet Accelerator ............................... 268
7.1 Memory Map Summary for 66AK2L06.............. 57
11.17 Security Accelerator .............................. 269
7.2 Memory Protection Unit (MPU)...................... 67
11.18 Network Coprocessor Gigabit Ethernet (GbE)
7.3 Interrupts for 66AK2L06............................. 80
Switch Subsystem ................................. 269
7.4 Enhanced Direct Memory Access (EDMA3)
11.19 SGMII Management Data Input/Output (MDIO) . 271
Controller for 66AK2L06 ........................... 128
11.20 Timers............................................. 272
8 System Interconnect ................................. 135
11.21 Rake Search Accelerator (RSA).................. 273
8.1 Internal Buses and Switch Fabrics ................ 135
11.22 General-Purpose Input/Output (GPIO) ........... 274
8.2 Switch Fabric Connections Matrix - Data Space .. 135
11.23 Semaphore2 ...................................... 275
8.3 TeraNet Switch Fabric Connections Matrix -
Configuration Space ............................... 147 11.24 IQNet (IQN)....................................... 275
8.4 Bus Priorities....................................... 155 11.25 Digital Front End (DFE)........................... 277
9 Device Boot and Configuration.................... 156 11.26 Fast Fourier Transform Coprocessor (FFTC) .... 278
9.1 Device Boot ........................................ 156 11.27 Universal Serial Bus 3.0 (USB 3.0)............... 278
9.2 Device Configuration............................... 174 11.28 Universal Subscriber Identity Module (USIM) .... 278
10 Device Operating Conditions ...................... 211 11.29 EMIF16 Peripheral................................ 278
10.1 Absolute Maximum Ratings........................ 211 11.30 Emulation Features and Capability ............... 281
10.2 Recommended Operating Conditions ............. 212 11.31 Debug Port (EMUx)............................... 284
10.3 Electrical Characteristics........................... 213 12 Mechanical Data ...................................... 294
10.4 Power Supply to Peripheral I/O Mapping.......... 214 12.1 Thermal Data ...................................... 294
11 66AK2L06 Peripheral Information and Electrical 12.2 Packaging Information ............................. 294
Specifications ......................................... 215
2 Revision History
DATE REVISION NOTES
March 2015 * Initial Release
Copyright © 2015, Texas Instruments Incorporated Revision History 5
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