MSMC
2MB
MSM
SRAM
72-Bit
DDR3 EMIF
Coprocessors
Boot ROM
Memory Subsystem
Packet
DMA
Multicore Navigator
Queue
Manager
3´ SPI
4´ UART
2´ PCIe
USB 3.0
5´
Debug & Trace
PLL
3´
Semaphore
EDMA
4´
EMIF16
Power
Management
GPIO 64´
66AK2L06
2´
FFTC
Network
Coprocessor
5-Port
Ethernet
Switch
Packet
Accelerator
Security
Accelerator
1GBE
1GBE
1GBE
1GBE
IQNet
3´ I C
2
4 C66x DSP Cores @ up to 1.2 GHz
2 ARM Cores @ up to 1.2 GHz
TeraNet
32KB L1
P-Cache
32KB L1
D-Cache
C66x™
CorePac
1024KB L2 Cache
RSA RSA
32KB L1
P-Cache
32KB L1
D-Cache
C66x™
CorePac
1024KB L2 Cache
RSA RSA
32KB L1
P-Cache
32KB L1
D-Cache
C66x™
CorePac
1024KB L2 Cache
RSA RSA
32KB L1
P-Cache
32KB L1
D-Cache
C66x™
CorePac
1024KB L2 Cache
RSA RSA
ARM
A15
1MB L2 Cache
32KB L1
P-Cache
32KB L1
D-Cache
ARM
A15
32KB L1
P-Cache
32KB L1
D-Cache
USIM
DFE
JESD204A/B
(2 Lanes)
JESD204A/B
(2 Lanes)
OSR
1MB
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
1.6 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Figure 1-1. Functional Block Diagram
Table of Contents
1 66AK2L06 Features and Description ................ 1 3.3 Development Tools ................................... 8
1.1 Features .............................................. 1 3.4 Device Nomenclature................................. 8
1.2 Applications........................................... 2 3.5 Related Documentation from Texas Instruments .... 9
1.3 KeyStone Architecture................................ 2 3.6 Community Resources .............................. 10
1.4 Device Description ................................... 2 3.7 Trademarks.......................................... 10
1.5 Enhancements in KeyStone II........................ 3 3.8 Electrostatic Discharge Caution..................... 10
1.6 Functional Block Diagram ............................ 4 3.9 Glossary ............................................. 10
2 Revision History ......................................... 5 4 C66x CorePac ........................................... 11
3 Device Characteristics.................................. 6 4.1 Memory Architecture ................................ 12
3.1 C66x DSP CorePac .................................. 7 4.2 Memory Protection .................................. 15
3.2 ARM CorePac ........................................ 7 4.3 Bandwidth Management ............................ 16
4 Table of Contents Copyright © 2015, Texas Instruments Incorporated
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