66AK2L06
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SPRS930 –APRIL 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
BALL
SIGNAL NAME NO. TYPE IPD/IPU DESCRIPTION
DDR3AD56 E30 IOZ
DDR3AD57 E29 IOZ
DDR3AD58 F29 IOZ
DDR3AD59 D30 IOZ
DDR3A EMIF data bus
DDR3AD60 C30 IOZ
DDR3AD61 D29 IOZ
DDR3AD62 B28 IOZ
DDR3AD63 A28 IOZ
DDR3ACE0 A14 OZ
DDR3A EMIF chip enable
DDR3ACE1 A11 OZ
DDR3ABA0 E11 OZ
DDR3ABA1 F12 OZ DDR3A EMIF bank address
DDR3ABA2 E12 OZ
DDR3AA00 C14 OZ
DDR3AA01 D14 OZ
DDR3AA02 A18 OZ
DDR3AA03 E14 OZ
DDR3A EMIF address bus
DDR3AA04 C15 OZ
DDR3AA05 A17 OZ
DDR3AA06 D15 OZ
DDR3AA07 B16 OZ
DDR3AA08 B17 OZ
DDR3AA09 D17 OZ
DDR3AA10 B12 OZ
DDR3AA11 B18 OZ
DDR3A EMIF address bus
DDR3AA12 C17 OZ
DDR3AA13 B11 OZ
DDR3AA14 E18 OZ
DDR3AA15 E16 OZ
DDR3ACAS A13 OZ DDR3A EMIF column address strobe
DDR3ARAS B13 OZ DDR3A EMIF row address strobe
DDR3AWE D12 OZ DDR3A EMIF write enable
DDR3ACKE0 E17 OZ DDR3A EMIF clock enable0
DDR3ACKE1 F17 OZ DDR3A EMIF clock enable1
DDR3ACLKOUTP0 A16 OZ
DDR3ACLKOUTN0 A15 OZ
DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM)
DDR3ACLKOUTP1 B15 OZ
DDR3ACLKOUTN1 B14 OZ
DDR3AODT0 A12 OZ
DDR3A EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3AODT1 F11 OZ
DDR3ARESET E15 OZ DDR3A reset signal
DDR3ARZQ0 F13 A PTV Compensation Reference Resistor PAD for DDR3A
DDR3ARZQ1 F9 A PTV Compensation Reference Resistor PAD for DDR3A
DDR3ARZQ2 F21 A PTV Compensation Reference Resistor PAD for DDR3A
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