C
T
PLH
A
B
3
1 2
A
C
B
Buffers
Buffer
Inputs
DP[n] /
EMU[n] Pins
T
PLH
66AK2L06
www.ti.com
SPRS930 –APRIL 2015
For more information on the AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(SPRA753)
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (SPRA387)
11.31.6 Trace
The device supports trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug
information for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for trace advanced emulation, see the Emulation and
Trace Headers Technical Reference Manual (SPRU655).
11.31.6.1 Trace Electrical Data/Timing
Table 11-77. Trace Switching Characteristics
(see Figure 11-68)
NO. PARAMETER MIN MAX UNIT
1 t
w
(DPnH) Pulse duration, DPn/EMUn high 2.4 ns
1 t
w
(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh 1.5 ns
2 t
w
(DPnL) Pulse duration, DPn/EMUn low 2.4 ns
2 t
w
(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh 1.5 ns
3 t
sko
(DPn) Output skew time, time delay difference between DPn/EMUn pins
-1 1 ns
configured as trace
t
skp
(DPn) Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-
600 ps
high (tplh) propagation delays.
t
sldp_o
(DPn) Output slew rate DPn/EMUn 3.3 V/ns
Figure 11-68. Trace Timing
11.31.7 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the
device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five
baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device
follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SGMII) support the
AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant
with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 291
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