66AK2L06
SPRS930 –APRIL 2015
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Table 11-74. Peripherals Emulation Support (continued)
EMULATION SUSPEND SUPPORT EMULATION
REQUEST DEBUG
STOP- REAL-TIME SUPPORT PERIPHERAL
PERIPHERAL MODE MODE FREE BIT STOP BIT (cemudbg/emudbg) ASSIGNMENT
Reserved
Reserved
Reserved
FFTC_0/1 Y Y Y Y N 47/48
IQN Y Y Y N N 53
Based on the above table the number of suspend interfaces in Keystone II devices is listed below.
Table 11-75. EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)
INTERFACES NUM_SUSPEND_PERIPHERALS
EMUSUSP Interfaces 54
EMUSUSP Realtime Interfaces 15
Table 11-76 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are
synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Table 11-76. EMUSUSP Core Summary (for EMUSUSP handshake to DEBUGSS)
CORE # ASSIGNMENT
0..3 C66x CorePac0..3
8,9 ARM CorePac 0,1
12..29 Reserved
30 Logical OR of Core #0..11
31 Logical AND of Core #0..11
11.31.5 Advanced Event Triggering (AET)
The device supports advanced event triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware program breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
290 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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