66AK2L06
SPRS930 –APRIL 2015
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Table 11-69. Emulation Interface with Different Debug Port Configurations (continued)
EMU CROSS DEBUG BOOT
PINS TRIGGERING ARM TRACE DSP TRACE STM MODE
EMU14 TRCDTa[10] TRCDTb[12] TRCDTa[10] TRCDTb[12] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU13 TRCDTa[9] TRCDTb[11] TRCDTa[9] TRCDTb[11] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU12 TRCDTa[8] TRCDTb[10] TRCDTa[8] TRCDTb[10] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU11 TRCDTa[7] TRCDTb[9] TRCDTa[7] TRCDTb[9] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU10 TRCDTa[6] TRCDTb[8] TRCDTa[6] TRCDTb[8] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU9 TRCDTa[5] TRCDTb[7] TRCDTa[5] TRCDTb[7] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU8 TRCDTa[4] TRCDTb[6] TRCDTa[4] TRCDTb[6] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU7 TRCDTa[3] TRCDTb[5] TRCDTa[3] TRCDTb[5] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU6 TRCDTa[2] TRCDTb[4] TRCDTa[2] TRCDTb[4] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU5 TRCDTa[1] TRCDTb[3] TRCDTa[1] TRCDTb[3] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU4 TRCDTa[0] TRCDTb[2] TRCDTa[0] TRCDTb[2] TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU3 TRCCTRL TRCCTRL TRCCLKB TRCCLKB TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU2 TRCCLK TRCCLK TRCCLKA TRCCLKA TRCDT3, or TRCDT2, or
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU1 Trigger1 TRCDTb[1] TRCDTb[1] TRCDT3, or TRCDT2, or dbgbootmode[1]
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU0 Trigger0 TRCDTb[0] TRCDTb[0] TRCDT3, or TRCDT2, or dbgbootmode[0]
TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
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