66AK2L06
SPRS930 –APRIL 2015
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
BALL
SIGNAL NAME NO. TYPE IPD/IPU DESCRIPTION
H29 IOZ Down
BOOTMODE08
B
J27 IOZ Down
BOOTMODE09
B
H28 IOZ Down
BOOTMODE10
B
User-defined boot mode pins. (
B
pins are secondary functions and are shared with GPIO[09:13])
G28 IOZ Down
BOOTMODE11
B
H27 IOZ Down
BOOTMODE12
B
AE5 I Down
BOOTMODE13
B
Select for the target core for LRESET and NMI. (
B
pin is a secondary function and is shared with
CORESEL0)
AG6 I Down
BOOTMODE14
B
User-defined boot mode pin. (
B
pin is a secondary function and is shared with CORESEL1)
AH6 I Down
BOOTMODE15
B
User-defined boot mode pin. (
B
pin is a secondary function and is shared with CORESEL2)
G26 IOZ Up
LENDIAN
B
Little endian configuration pin. (
B
pin is a secondary function and is shared with GPIO00)
J30 IOZ Down
MAINPLL_OD_SEL
B
Main PLL output divider select. (
B
pin is a secondary function and is shared with GPIO14)
Clock / Reset
ALTCORECLKN AH30 I
System clock input to antenna interface and main PLL (Main PLL optional vs. ALTCORECLK)
ALTCORECLKP AG30 I
BOOTCOMPLETE AG3 O Down Boot progress indication output
CORECLKSEL0 AE27 I Down
Ref clock select for core/ARM/PA PLL
CORECLKSEL1 AF27 I Down
CORESEL0 AE5 I Down
CORESEL1 AG6 I Down Select for the target core for LRESET and NMI
CORESEL2 AH6 I Down
DDR3ACLKN G30 I
DDR3A reference clock input to DDR PLL
DDR3ACLKP F30 I
HOUT AH2 O Up Interrupt output pulse created by IPCGRH
LRESET AK3 I Up Warm reset
LRESETNMIEN AF2 I Up Enable for core selects
NMI AJ2 I Up Non-maskable interrupt
PCIECLKN AE19 I
PCIe reference clock to drive the PCIe SerDes. Not used when PCIe is not selected
PCIECLKP AE20 I
POR G4 I Power-on reset
RESET AF3 I Up Warm reset of non isolated portion on the IC
RESETFULL AE2 I Up Full reset
RESETSTAT AE4 O Up Reset status output. Drives low during power-on reset (no HHV override). Available after core and IOs
are are completely powered-up.
SGMIICLKN AF24 I
SGMII reference clock to drive the SGMII SerDes
SGMIICLKP AF23 I
SYSCLKN AG29 I
System clock input to antenna interface and main PLL (Main PLL optional vs. ALTCORECLK)
SYSCLKP AF29 I
SYSCLKOUT AF28 O Down System clock output to be used as a general purpose output clock for debug purposes
TSREFCLKN AK14 I
Clock from external OCXO/VCXO for SyncE
TSREFCLKP AK13 I
TSRXCLKOUT0N AJ13 O
SerDes recovered clock output for SyncE.
TSRXCLKOUT0P AJ12 O
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