66AK2L06
SPRS930 –APRIL 2015
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• Digital Pre-Distortion (DPD) Support
• Crest Factor Reduction (CFR) Support
11.26 Fast Fourier Transform Coprocessor (FFTC)
There are two Fast Fourier Transform Coprocessors (FFTC) used to accelerate FFT, IFFT, DFT, and IDFT
operations. For more information, see the KeyStone Architecture Fast Fourier Transform Coprocessor
(FFTC) User's Guide (SPRUGS2).
11.27 Universal Serial Bus 3.0 (USB 3.0)
The device includes a USB 3.0 controller providing the following capabilities:
• Support of USB 3.0 peripheral (or device) mode at the following speeds:
– Super Speed (SS) (5 Gbps)
– High Speed (HS) (480 Mbps)
– Full Speed (FS) (12 Mbps)
• Support of USB 3.0 host mode at the following speeds:
– Super Speed (SS) (5 Gbps)
– High Speed (HS) (480 Mbps)
– Full Speed (FS) (12 Mbps)
– Low Speed (LS) (1.5 Mbps)
• Integrated DMA controller with extensible Host Controller Interface (xHCI) support
• Support for 14 transmit and 14 receive endpoints plus control EP0
For more information, see the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
(SPRUHJ7).
11.28 Universal Subscriber Identity Module (USIM)
The 66AK2L06 is equipped with a Universal Subscriber Identity Module (USIM) for user authentication.
The USIM is compatible with ISO, ETSI/GSM, and 3GPP standards.
The USIM is implemented for support of secure devices only. Contact your local technical sales
representative for further details.
11.29 EMIF16 Peripheral
The EMIF16 module provides an interface between the device and external memories such as NAND and
NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16)
User's Guide (SPRUGZ3).
11.29.1 EMIF16 Electrical Data/Timing
Table 11-67. EMIF16 Asynchronous Memory Timing Requirements
(1)
(see Figure 11-64 through Figure 11-67)
NO. MIN MAX UNIT
General Timing
2 t
w
(WAIT) Pulse duration, WAIT assertion and deassertion minimum time 2E ns
28 t
d
(WAIT-WEH) Setup time, WAIT asserted before WE high 4E + 3 ns
14 t
d
(WAIT-OEH) Setup time, WAIT asserted before OE high 4E + 3 ns
Read Timing
3 EMIF read cycle time when ew = 0, meaning not in extended wait (RS+RST+RH+3) (RS+RST+RH+3) ns
t
C
(CEL)
mode *E-3 *E+3
3 EMIF read cycle time when ew =1, meaning extended wait mode (RS+RST+RH+3) (RS+RST+RH+3) ns
t
C
(CEL)
enabled *E-3 *E+3
(1) E = 1/(SYSCLK1/6)
278 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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