66AK2L06
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SPRS930 –APRIL 2015
Figure 11-61. AIF Physical Layer Synchronization Pulse Timing
Figure 11-62. AIF Radio Synchronization Pulse Timing
Table 11-66. AIF Timer Module Switching Characteristics
(see Figure 11-63)
NO. PARAMETER MIN MAX UNIT
External Frame Event
14 tw(EXTFRAMEEVENTH) Pulse width, EXTFRAMEEVENT output high 8 * C1
(1)
ns
15 tw(EXTFRAMEEVENTL) Pulse width, EXTFRAMEEVENT output low 8 * C1 ns
(1) C1 = 245.76MHz clock for CPRI and 307.2MHz clock for OBSAI.
Figure 11-63. AIF Timer External Frame Event Timing
11.25 Digital Front End (DFE)
The 66AK2L06 integrates the Digital Front-End (DFE) subsystem with Digital Down/Up-Conversion
(DDC/DUC) functionality. The DFE subsystem provides a direct interface to high-speed analog-to-digital
and digital-to-analog data converters and analog front end.
• Support for JESD204A/B
– Support for Four Tx and Four Rx 7.37Gbps lanes
– Alignment across multiple lanes within a single converter or multiple converters in the same device
– Support for Subclass 0 and 1 (Subclass 2 is not supported)
– Deterministic latency using SYSREF signaling
– Backward compatibility with JESD204A
• DFE clock frequency of 245.76 MHz and 368.64 MHz
• 8-bit DVGA interface (pin muxed with DFE GPIO)
• 16 DFE GPIOs to interface to Digital Variable Gain Amplifiers (DVGA), RF muxes, Power amplifier
(PA) Time Division Duplex (TDD) controls. These GPIOs are different from the chip-level GPIOs. The
DFE GPIOs are controlled directly by the DFE MMRs.
• DUC/DDC, RX integrated
The following features are specified in the DFE user's guide, but are not supported in this device:
• Back-end Automatic Gain Control (AGC) Support
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 277
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