RP1FBP/N
7
RP1 Frame Burst BIT 0
6
RP1 Frame Burst BIT 2 RP1 Frame Burst BIT N
RP1CLKP
RP1CLKN
8 9
66AK2L06
SPRS930 –APRIL 2015
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Table 11-65. AIF Timer Module Timing Requirements (continued)
(see Figure 11-59, Figure 11-60, Figure 11-61, and Figure 11-62)
NO. MIN MAX UNIT
4 tr(RP1CLKP) Rise time - RP1CLKP 10% to 90% 350.00 ps
4 tf(RP1CLKP) Fall time - RP1CLKP 90% to 10% 350.00 ps
5 tj(RP1CLKN) Period jitter (peak-to-peak), RP1CLK(N) 600 ps
5 tj(RP1CLKP) Period jitter (peak-to-peak), RP1CLK(P) 600 ps
6 tw(RP1FBN) Bit period, RP1FB(N) 8 * C1 8 * C1 ns
6 tw(RP1FBP) Bit period, RP1FB(P) 8 * C1 8 * C1 ns
7 tr(RP1CLKN) Rise time - RP1FBN 10% to 90% 350.00 ps
7 tf(RP1CLKN) Fall time - RP1FBN 90% to 10% 350.00 ps
7 tr(RP1CLKP) Rise time - RP1FBP 10% to 90% 350.00 ps
7 tf(RP1CLKP) Fall time - RP1FBP 90% to 10% 350.00 ps
8 tsu(RP1FBN-RP1CLKP) Setup time - RP1FBN valid before RP1CLKP high 2 ns
8 tsu(RP1FBN-RP1CLKN) Setup time - RP1FBN valid before RP1CLKN low 2 ns
8 tsu(RP1FBN-RP1CLKP) Setup time - RP1FBP valid before RP1CLKP high 2 ns
8 tsu(RP1FBN-RP1CLKN) Setup time - RP1FBP valid before RP1CLKN low 2 ns
9 th(RP1FBN-RP1CLKP) Hold time - RP1FBN valid after RP1CLKP high 2 ns
9 th(RP1FBN-RP1CLKN) Hold time - RP1FBN valid after RP1CLKN low 2 ns
9 th(RP1FBN-RP1CLKP) Hold time - RP1FBP valid after RP1CLKP high 2 ns
9 th(RP1FBN-RP1CLKN) Hold time - RP1FBP valid after RP1CLKN low 2 ns
PHY Sync and Radio Sync Pulses
10 tw(PHYSYNCH) Pulse duration, PHYSYNC high 6.50 ns
11 tc(PHYSYNC) Cycle time, PHYSYNC pulse to PHYSYNC pulse 10.00 ms
12 tw(RADSYNCH) Pulse duration, RADSYNC high 6.50 ns
13 tc(RADSYNC) Cycle time, RADSYNC pulse to RADSYNC pulse 1.00 ms
Figure 11-59. AIF RP1 Frame Synchronization Clock Timing
Figure 11-60. AIF RP1 Frame Synchronization Burst Timing
276 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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