8
TXD Bit N-1 Bit N Stop Start Bit 0
CTS
65
5
4
Stop/Idle
RXD Start Bit 0
Bit 1 Bit N-1 Bit N Parity Stop Idle Start
66AK2L06
www.ti.com
SPRS930 –APRIL 2015
11.14 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the device
and a UART terminal interface or other UART-based peripheral. The UART is based on the industry
standard TL16C550 asynchronous communications element which, in turn, is a functional upgrade of the
TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the
UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the SoC of excessive software
overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to
16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the SoC CorePacs to be sent to the peripheral device. The SoC
CorePacs can read the UART status at any time. The UART includes control capability and a processor
interrupt system that can be tailored to minimize software management of the communications link. For
more information on UART, see the KeyStone Architecture Universal Asynchronous Receiver/Transmitter
(UART) User's Guide (SPRUGP1).
Table 11-52. UART Timing Requirements
(see Figure 11-48 and Figure 11-49)
NO. MIN MAX UNIT
Receive Timing
4 tw(RXSTART) Pulse width, receive start bit 0.96U
(1)
1.05U ns
5 tw(RXH) Pulse width, receive data/parity bit high 0.96U 1.05U ns
5 tw(RXL) Pulse width, receive data/parity bit low 0.96U 1.05U ns
6 tw(RXSTOP1) Pulse width, receive stop bit 1 0.96U 1.05U ns
6 tw(RXSTOP15) Pulse width, receive stop bit 1.5 0.96U 1.05U ns
6 tw(RXSTOP2) Pulse width, receive stop bit 2 0.96U 1.05U ns
Autoflow Timing Requirements
8 td(CTSL-TX) Delay time, CTS asserted to START bit transmit P
(2)
5P ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
Figure 11-48. UART Receive Timing Waveform
Figure 11-49. UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 267
Submit Documentation Feedback
Product Folder Links: 66AK2L06
