MASTER MODE 4 PIN WITH CHIP SELECT
SPICLK
SPIDOUT
SPIDIN
SPISCSx
MO(0)
MO(1)
MO(n−1)
MO(n)
MI(0) MI(1) MI(n−1) MI(n)
19 20
SPICLK
SPIDOUT
SPIDIN
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
6
6
7
7
7
7
8
8
8
8
32
6
1
4
4
4
4
5
5
5
6
MASTER MODE
POLARITY = 0 PHASE = 0
MASTER MODE
POLARITY = 0 PHASE = 1
MASTER MODE
POLARITY = 1 PHASE = 0
MASTER MODE
POLARITY = 1 PHASE = 1
5
SPICLK
SPIDOUT
SPIDIN
SPICLK
SPIDOUT
SPIDIN
SPICLK
SPIDOUT
SPIDIN
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Figure 11-46. SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
Figure 11-47. SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
266 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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