66AK2L06
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SPRS930 –APRIL 2015
Table 11-51. SPI Switching Characteristics (continued)
(see Figure 11-46 and Figure 11-47)
NO. PARAMETER MIN MAX UNIT
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge ns
5
on SPICLK Polarity = 1, Phase = 1
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to ns
2
initial edge on SPICLK. Polarity = 0 Phase = 0
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to ns
2
initial edge on SPICLK Polarity = 0 Phase = 1
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to ns
2
initial edge on SPICLK Polarity = 1 Phase = 0
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to ns
2
initial edge on SPICLK Polarity = 1 Phase = 1
6 toh(SPC- Output hold time, SPIDOUT valid after receive edge of ns
0.5*tc - 2
SPIDOUT) SPICLK except for final bit. Polarity = 0 Phase = 0
6 toh(SPC- Output hold time, SPIDOUT valid after receive edge of ns
0.5*tc - 2
SPIDOUT) SPICLK except for final bit. Polarity = 0 Phase = 1
6 toh(SPC- Output hold time, SPIDOUT valid after receive edge of ns
0.5*tc - 2
SPIDOUT) SPICLK except for final bit. Polarity = 1 Phase = 0
6 toh(SPC- Output hold time, SPIDOUT valid after receive edge of ns
0.5*tc - 2
SPIDOUT) SPICLK except for final bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 0 ns
2*P2 - 5 2*P2 + 5
Phase = 0
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 0 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5
Phase = 1
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 1 ns
2*P2 - 5 2*P2 + 5
Phase = 0
19 td(SCS-SPC) Delay from SPISCSx\ active to first SPICLK. Polarity = 1 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5
Phase = 1
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting ns
1*P2 - 5 1*P2 + 5
SPISCSx\. Polarity = 0 Phase = 0
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting ns
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
SPISCSx\. Polarity = 0 Phase = 1
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting ns
1*P2 - 5 1*P2 + 5
SPISCSx\. Polarity = 1 Phase = 0
20 td(SPC-SCS) Delay from final SPICLK edge to master deasserting ns
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
SPISCSx\. Polarity = 1 Phase = 1
tw(SCSH) Minimum inactive time on SPISCSx\ pin between two transfers ns
2*P2 - 5
when SPISCSx\ is not held using the CSHOLD feature.
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