66AK2L06
SPRS930 –APRIL 2015
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Table 11-47. I
2
C Registers (continued)
HEX ADDRESS OFFSETS ACRONYM REGISTER NAME
0x003C -0x007F - Reserved
11.12.3 I
2
C Electrical Data/Timing
11.12.3.1 Inter-Integrated Circuits (I
2
C) Timing
Table 11-48. I
2
C Timing Requirements
(1)
(see Figure 11-44)
STANDARD MODE FAST MODE
NO. MIN MAX MIN MAX UNIT
1 t
c(SCL)
Cycle time, SCL 10 2.5 µs
2 Setup time, SCL high before SDA low (for a repeated START
t
su(SCLH-SDAL)
4.7 0.6 µs
condition)
3 Hold time, SCL low after SDA low (for a START and a
t
h(SDAL-SCLL)
4 0.6 µs
repeated START condition)
4 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
5 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
6 t
su(SDAV-SCLH)
Setup time, SDA valid before SCL high 250 100
(2)
ns
7 t
h(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I
2
C bus devices) 0
(3)
3.45 0
(3)
0.9
(4)
µs
8 Pulse duration, SDA high between STOP and START
t
w(SDAH)
4.7 1.3 µs
conditions
9 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(5)
300 ns
10 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(5)
300 ns
11 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(5)
300 ns
12 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(5)
300 ns
13 t
su(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 t
w(SP)
Pulse duration, spike (must be suppressed) 0 50 ns
C
b
(5)
Capacitive load for each bus line 400 400 pF
(1) The I
2
C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
r
max + t
su(SDA-SCLH)
= 1000 + 250 = 1250 ns
(according to the Standard-mode I
2
C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t
h(SDA-SCLL)
has to be met only if the device does not stretch the low period [t
w(SCLL)
] of the SCL signal.
(5) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
262 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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